//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __COMM_HW_H__
#define __COMM_HW_H__


/*
 * Bulverde Definitions
 */
#define v_PerifBase (0x80000000)  /*KCONFIG_MEMORY_MAPPED_IO_BASE*/

#if defined(__HAVENOT_USEMMU)
#define __REG(x)    (*(volatile int *)(x))
#else
#define __REG(x)    (*(volatile int *) (((x)- 0x40000000)+(unsigned long)v_PerifBase))
#endif


/* GPIO registers */

#define GPLR0       __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
#define GPLR1       __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
#define GPLR2       __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<95:64> */

#define GPDR0       __REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
#define GPDR1       __REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
#define GPDR2       __REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<95:64> */

#define GPSR0       __REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
#define GPSR1       __REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
#define GPSR2       __REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<95:64> */

#define GPCR0       __REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
#define GPCR1       __REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
#define GPCR2       __REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <95:64> */

#define GRER0       __REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
#define GRER1       __REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
#define GRER2       __REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<95:64> */

#define GFER0       __REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
#define GFER1       __REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
#define GFER2       __REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<95:64> */

#define GEDR0       __REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
#define GEDR1       __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
#define GEDR2       __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<95:64> */

#define GAFR0_L     __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
#define GAFR0_U     __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
#define GAFR1_L     __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
#define GAFR1_U     __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
#define GAFR2_L     __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U     __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO <95:80> */
#define GAFR3_L     __REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
#define GAFR3_U     __REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO <120:112> */

#define GPLR3       __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<120:96> */
#define GPDR3       __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<120:96> */
#define GPSR3       __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<120:96> */
#define GPCR3       __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO <120:96> */
#define GRER3       __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<120:96> */
#define GFER3       __REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<120:96> */
#define GEDR3       __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<120:96> */


/******************************************************************/
/*   Peripheral OFFSETS                                           */
/******************************************************************/
#define CLK_ENABLE  __REG(0x41300004)

/*
 * Core Clock
 */
#define OSCC		__REG(0x41300008)

#define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
#define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
#define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */

#define BTLCR       __REG(0x4020000C)  /* Line Control Register (read/write) */

int module_on2pc_gpio_init();
int module_gpio_init();

int module_power_on();
int module_power_off();
int module_wake_up();
int module_sleep();
int module_is_sleeping();

int bluetooth_power_on();
int bluetooth_power_off();
int bluetooth_wake_up();
int bluetooth_sleep();

#endif // __COMM_HW_H__

